1. Field of the Invention
The present invention relates to an ESD (Electro-Static Discharge) protection circuit for a semiconductor device and a method for fabricating the same that simplifies the fabrication process.
2. Discussion of the Related Art
In general, all current semiconductor devices use salicides to reduce circuit operation speeds. However, in order to provide an appropriate ballistic resistance required for a performance of an ESD protection circuit of a high failure voltage, a salicide protection mask is applied to prevent formation of a salicide in a region to be used as the ESD protection circuit.
A conventional ESD protection circuit and a conventional method for fabricating the same will be explained with reference to the attached drawings.
FIG. 1 illustrates a lay-out of the conventional ESD protection circuit, and FIG. 2 illustrates a section across line II--II in FIG. 1. Referring to FIGS. 1 and 2, the conventional ESD protection circuit includes isolating films 12 of STI (Shallow Trench Isolation) structures formed in field regions of a semiconductor substrate 11 having an active region and field regions defined thereon, and a gate insulating film 13 and a gate electrode 14a formed in the active region of the semiconductor substrate 11. Insulating sidewalls 16 are formed at both sides of the gate electrode 14a. First and second heavily doped n-type impurity regions 17a and 17b are formed in a surface of the semiconductor substrate 11 on both sides of the gate electrode 14a. A planarizing layer 18 is formed with contact holes 19 exposing surfaces of the first and second heavily doped n-type impurity regions 17a and 17b. Metal wiring 20 electrically connects the first and second heavily doped n-type impurity regions 17a and 17b through the contact holes 19. A salicide protection mask 10 masks the ESD protection circuit region during formation of a salicide film on a region other than the ESD protection circuit region.
FIGS. 3A-3F illustrate sections across line II--II of FIG. 1 showing the steps of a conventional method for fabricating an ESD protection circuit.
Referring to FIG. 3A, trenches are formed in field regions of the semiconductor substrate 11 having the active region and the field regions defined thereon to prescribed depths. An insulating film is formed on an entire surface of the semiconductor substrate 11 including the trenches, and is partly removed by etch back or CMP (Chemical Mechanical Polishing) to leave the insulating film only in the trenches, forming the isolating films 12 of the STI structures. As shown in FIG. 3B, the gate insulating film 13 and a gate electrode polysilicon layer 14 are formed on an entire surface of the semiconductor substrate 11 including the isolating films 12. A photoresist 15 is coated on the polysilicon layer 14 and patterned by exposure and development to define a gate region. As shown in FIG. 3C, the polysilicon layer 14 and the gate insulating film 13 are selectively removed using the patterned photoresist 15 as a mask, forming the gate electrode 14a. As shown in FIG. 3D, an insulating film is formed on an entire surface of the semiconductor substrate 11 including the gate electrode 14a, and is etched back to form the insulating sidewalls 16 at both sides of the gate electrodes 14a. Then, a high concentration of n-type impurity ions is injected into the semiconductor substrate 11 using the gate electrode 14a and the insulating film sidewalls 16 as masks, to form the first and second heavily doped n-type impurity regions 17a and 17b in the surface of the semiconductor substrate 11 on both sides of the gate electrode 14a. As shown in FIG. 1, after forming the salicide protection mask 10 such that a salicide film will not be formed in the ESD protection circuit, a salicide material is deposited on regions outside the ESD protection circuit region, and is annealed to form the salicide film, and the salicide protection mask 10 is then removed and cleaned. As shown in FIG. 3E, a planarizing layer 18 of BPSG (Boron Phosphorus Silicate Glass) or SOG (Spin On Glass) is formed on an entire surface of the semiconductor substrate 11 and selectively removed by photolithography and etching, forming contact holes 19 exposing surfaces of the first and second heavily doped n-type impurity regions 17a and 17b. As shown in FIG. 3F, a metal layer is deposited on the planarizing layer 18 and in the contact holes 19 and selectively patterned, forming the metal wiring 20 electrically connecting the surfaces of the first and second heavily doped n-type impurity regions 17a and 17b through the contact holes 19.
However, the conventional ESD protection circuit and manufacturing method have the following problems.
First, the formation of a salicide protection mask only on a region that operates as an ESD protection circuit increases the number of fabrication steps and the cost of fabrication.
Second, the over etch of the STI material during removing and cleaning of the salicide protection mask causes a sharp increase of a junction leakage current, thus degrading electrical performance of the device.